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Ward Nakchbandi (Cosmic Fusion) 2023-10-05 22:46:05 +03:00 committed by GitHub
parent cd314076ee
commit c359a99e0a
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16 changed files with 154 additions and 629 deletions
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2
debian/changelog vendored
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@ -1,4 +1,4 @@
mesa (23.1.9-100pika2) pikauwu; urgency=medium
mesa (23.2.1-100pika2) pikauwu; urgency=medium
* Initial Release

42
debian/patches/0001_radv_amdgpu:_Remove_unnecessary_assertions_from_chaining..patch vendored
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@ -1,42 +0,0 @@
From add3b34c171821804049084cf9d252a72cc54e2b Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Timur=20Krist=C3=B3f?= <timur.kristof@gmail.com>
Date: Tue, 11 Apr 2023 13:59:49 +0200
Subject: radv/amdgpu: Remove unnecessary assertions from chaining.
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
These used to guard against chaining on GFX6 and on HW IP types
that don't support chaining, but these things are now guarded
elsewhere and these assertions are no longer necessary.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22406>
---
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
index 7107fc0b896..1b8f9b86c34 100644
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
@@ -482,7 +482,6 @@ radv_amdgpu_cs_unchain(struct radeon_cmdbuf *cs)
return;
assert(cs->cdw <= cs->max_dw + 4);
- assert(get_nop_packet(acs) == PKT3_NOP_PAD); /* Other shouldn't chain. */
acs->chained_to = NULL;
cs->buf[cs->cdw - 4] = PKT3_NOP_PAD;
@@ -511,7 +510,6 @@ radv_amdgpu_cs_chain(struct radeon_cmdbuf *cs, struct radeon_cmdbuf *next_cs, bo
return false;
assert(cs->cdw <= cs->max_dw + 4);
- assert(get_nop_packet(acs) == PKT3_NOP_PAD); /* Other shouldn't chain. */
acs->chained_to = next_acs;
--
cgit v1.2.1

33
debian/patches/0002_radv:_Disallow_IB2_on_GFX6_when_using_draw_indirect_multi..patch vendored
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@ -1,33 +0,0 @@
From 0e7244ce1848978022cb6f24683eb2cfdfd7fbbb Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Timur=20Krist=C3=B3f?= <timur.kristof@gmail.com>
Date: Tue, 11 Apr 2023 02:29:38 +0200
Subject: radv: Disallow IB2 on GFX6 when using draw_indirect_multi.
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
GFX6 has the same problem as GFX7 here.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22406>
---
src/amd/vulkan/radv_cmd_buffer.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 8eae45769ab..cb031b95173 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -7498,7 +7498,7 @@ radv_CmdExecuteCommands(VkCommandBuffer commandBuffer, uint32_t commandBufferCou
RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
bool allow_ib2 = true;
- if (secondary->device->physical_device->rad_info.gfx_level == GFX7 &&
+ if (secondary->device->physical_device->rad_info.gfx_level <= GFX7 &&
secondary->state.uses_draw_indirect_multi) {
/* Do not launch an IB2 for secondary command buffers that contain
* DRAW_{INDEX}_INDIRECT_MULTI on GFX7 because it's illegal and hang the GPU.
--
cgit v1.2.1

36
debian/patches/0003_radv:_Use_IB_BOs_(chaining)_by_default_on_GFX6..patch vendored
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@ -1,36 +0,0 @@
From d6518fd3571e315a7a7e62af5e1abbfdb3a3b97b Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Timur=20Krist=C3=B3f?= <timur.kristof@gmail.com>
Date: Tue, 11 Apr 2023 02:30:10 +0200
Subject: radv: Use IB BOs (chaining) by default on GFX6.
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
GFX6 supports IB chaining since the PFP firmware version 20.
Note that the very first amdgpu firmware for GFX6 already had
version 29, so we can assume that all GPUs supported by RADV
have this feature.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22406>
---
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c
index ec85e7249c4..c944d2d422e 100644
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c
@@ -62,7 +62,7 @@ do_winsys_init(struct radv_amdgpu_winsys *ws, int fd)
ws->info.ip[AMD_IP_SDMA].num_queues = MIN2(ws->info.ip[AMD_IP_SDMA].num_queues, MAX_RINGS_PER_TYPE);
ws->info.ip[AMD_IP_COMPUTE].num_queues = MIN2(ws->info.ip[AMD_IP_COMPUTE].num_queues, MAX_RINGS_PER_TYPE);
- ws->use_ib_bos = ws->info.gfx_level >= GFX7;
+ ws->use_ib_bos = true;
return true;
}
--
cgit v1.2.1

46
debian/patches/0004_radv:_Chain_command_buffers_on_GFX6_in_radv_queue..patch vendored
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@ -1,46 +0,0 @@
From 7ddac41f3f5919be748143d8a570cc3b1f4ed27c Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Timur=20Krist=C3=B3f?= <timur.kristof@gmail.com>
Date: Tue, 11 Apr 2023 02:31:28 +0200
Subject: radv: Chain command buffers on GFX6 in radv_queue.
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Also don't check whether chaining is enabled in radv_queue, the
winsys will take care of that anyway.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22406>
---
src/amd/vulkan/radv_queue.c | 7 ++-----
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/src/amd/vulkan/radv_queue.c b/src/amd/vulkan/radv_queue.c
index 0823e545a19..e00d448ed18 100644
--- a/src/amd/vulkan/radv_queue.c
+++ b/src/amd/vulkan/radv_queue.c
@@ -1693,9 +1693,6 @@ radv_queue_submit_normal(struct radv_queue *queue, struct vk_queue_submit *submi
.uses_shadow_regs = queue->state.uses_shadow_regs,
};
- const bool chaining_en = !(queue->device->instance->debug_flags & RADV_DEBUG_NO_IBS) &&
- queue->device->physical_device->rad_info.gfx_level >= GFX7;
-
for (uint32_t j = 0, advance; j < cmd_buffer_count; j += advance) {
advance = MIN2(max_cs_submission, cmd_buffer_count - j);
const bool last_submit = j + advance == cmd_buffer_count;
@@ -1714,8 +1711,8 @@ radv_queue_submit_normal(struct radv_queue *queue, struct vk_queue_submit *submi
struct radv_cmd_buffer *cmd_buffer =
(struct radv_cmd_buffer *)submission->command_buffers[j + c];
assert(cmd_buffer->vk.level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
- const bool can_chain_next = chaining_en && !(cmd_buffer->usage_flags &
- VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT);
+ const bool can_chain_next =
+ !(cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT);
/* ACE needs to be first because the last CS must match the queue's IP type. */
if (radv_cmd_buffer_needs_ace(cmd_buffer)) {
--
cgit v1.2.1

153
debian/patches/0005_amd:_Rename_INDIRECT_BUFFER_CIK_to_just_INDIRECT_BUFFER..patch vendored
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@ -1,153 +0,0 @@
From 948a122f300b3df036fea1a8e14301295062e360 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Timur=20Krist=C3=B3f?= <timur.kristof@gmail.com>
Date: Thu, 13 Apr 2023 17:23:40 +0200
Subject: amd: Rename INDIRECT_BUFFER_CIK to just INDIRECT_BUFFER.
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
This packet is supported on GFX6 too, its name should relect that.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22406>
---
src/amd/common/ac_debug.c | 2 +-
src/amd/common/sid.h | 2 +-
src/amd/vulkan/radv_cmd_buffer.c | 6 +++---
src/amd/vulkan/radv_cp_reg_shadowing.c | 2 +-
src/amd/vulkan/radv_queue.c | 2 +-
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c | 6 +++---
src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 2 +-
7 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/src/amd/common/ac_debug.c b/src/amd/common/ac_debug.c
index 9c0d9436f48..3503ff23f5c 100644
--- a/src/amd/common/ac_debug.c
+++ b/src/amd/common/ac_debug.c
@@ -449,7 +449,7 @@ static void ac_parse_packet3(FILE *f, uint32_t header, struct ac_ib_parser *ib,
break;
case PKT3_INDIRECT_BUFFER_SI:
case PKT3_INDIRECT_BUFFER_CONST:
- case PKT3_INDIRECT_BUFFER_CIK: {
+ case PKT3_INDIRECT_BUFFER: {
uint32_t base_lo_dw = ac_ib_get(ib);
ac_dump_reg(f, ib->gfx_level, ib->family, R_3F0_IB_BASE_LO, base_lo_dw, ~0);
uint32_t base_hi_dw = ac_ib_get(ib);
diff --git a/src/amd/common/sid.h b/src/amd/common/sid.h
index 5bc60316c82..0c860c1acbd 100644
--- a/src/amd/common/sid.h
+++ b/src/amd/common/sid.h
@@ -132,7 +132,7 @@
#define WAIT_REG_MEM_MEM_SPACE(x) (((unsigned)(x)&0x3) << 4)
#define WAIT_REG_MEM_PFP (1 << 8)
#define PKT3_MEM_WRITE 0x3D /* GFX6 only */
-#define PKT3_INDIRECT_BUFFER_CIK 0x3F /* GFX7+ */
+#define PKT3_INDIRECT_BUFFER 0x3F /* GFX6+ */
#define PKT3_COPY_DATA 0x40
#define COPY_DATA_SRC_SEL(x) ((x)&0xf)
#define COPY_DATA_REG 0
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index cb031b95173..343cd6ca9f8 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -9509,7 +9509,7 @@ radv_CmdExecuteGeneratedCommandsNV(VkCommandBuffer commandBuffer, VkBool32 isPre
return;
/* Secondary command buffers are needed for the full extension but can't use
- * PKT3_INDIRECT_BUFFER_CIK.
+ * PKT3_INDIRECT_BUFFER.
*/
assert(cmd_buffer->vk.level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
@@ -9539,7 +9539,7 @@ radv_CmdExecuteGeneratedCommandsNV(VkCommandBuffer commandBuffer, VkBool32 isPre
radeon_emit(cmd_buffer->cs, 0);
if (!view_mask) {
- radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
+ radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER, 2, 0));
radeon_emit(cmd_buffer->cs, va);
radeon_emit(cmd_buffer->cs, va >> 32);
radeon_emit(cmd_buffer->cs, cmdbuf_size >> 2);
@@ -9547,7 +9547,7 @@ radv_CmdExecuteGeneratedCommandsNV(VkCommandBuffer commandBuffer, VkBool32 isPre
u_foreach_bit (view, view_mask) {
radv_emit_view_index(cmd_buffer, view);
- radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
+ radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER, 2, 0));
radeon_emit(cmd_buffer->cs, va);
radeon_emit(cmd_buffer->cs, va >> 32);
radeon_emit(cmd_buffer->cs, cmdbuf_size >> 2);
diff --git a/src/amd/vulkan/radv_cp_reg_shadowing.c b/src/amd/vulkan/radv_cp_reg_shadowing.c
index 3f46b7c1619..dac9411c03b 100644
--- a/src/amd/vulkan/radv_cp_reg_shadowing.c
+++ b/src/amd/vulkan/radv_cp_reg_shadowing.c
@@ -112,7 +112,7 @@ radv_emit_shadow_regs_preamble(struct radeon_cmdbuf *cs, const struct radv_devic
struct radv_queue_state *queue_state)
{
uint64_t va = radv_buffer_get_va(queue_state->shadow_regs_ib);
- radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
+ radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER, 2, 0));
radeon_emit(cs, va);
radeon_emit(cs, va >> 32);
radeon_emit(cs, queue_state->shadow_regs_ib_size_dw & 0xffff);
diff --git a/src/amd/vulkan/radv_queue.c b/src/amd/vulkan/radv_queue.c
index e00d448ed18..b28797547be 100644
--- a/src/amd/vulkan/radv_queue.c
+++ b/src/amd/vulkan/radv_queue.c
@@ -828,7 +828,7 @@ radv_init_graphics_state(struct radeon_cmdbuf *cs, struct radv_device *device)
if (device->gfx_init) {
uint64_t va = radv_buffer_get_va(device->gfx_init);
- radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
+ radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER, 2, 0));
radeon_emit(cs, va);
radeon_emit(cs, va >> 32);
radeon_emit(cs, device->gfx_init_size_dw & 0xffff);
diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
index 1b8f9b86c34..1caa359ebe6 100644
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
@@ -372,7 +372,7 @@ radv_amdgpu_cs_grow(struct radeon_cmdbuf *_cs, size_t min_size)
cs->ws->base.cs_add_buffer(&cs->base, cs->ib_buffer);
if (cs->use_ib) {
- radeon_emit(&cs->base, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
+ radeon_emit(&cs->base, PKT3(PKT3_INDIRECT_BUFFER, 2, 0));
radeon_emit(&cs->base, radv_amdgpu_winsys_bo(cs->ib_buffer)->base.va);
radeon_emit(&cs->base, radv_amdgpu_winsys_bo(cs->ib_buffer)->base.va >> 32);
radeon_emit(&cs->base, S_3F2_CHAIN(1) | S_3F2_VALID(1));
@@ -513,7 +513,7 @@ radv_amdgpu_cs_chain(struct radeon_cmdbuf *cs, struct radeon_cmdbuf *next_cs, bo
acs->chained_to = next_acs;
- cs->buf[cs->cdw - 4] = PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0);
+ cs->buf[cs->cdw - 4] = PKT3(PKT3_INDIRECT_BUFFER, 2, 0);
cs->buf[cs->cdw - 3] = next_acs->ib.ib_mc_address;
cs->buf[cs->cdw - 2] = next_acs->ib.ib_mc_address >> 32;
cs->buf[cs->cdw - 1] =
@@ -667,7 +667,7 @@ radv_amdgpu_cs_execute_secondary(struct radeon_cmdbuf *_parent, struct radeon_cm
radv_amdgpu_cs_grow(&parent->base, 4);
/* Not setting the CHAIN bit will launch an IB2. */
- radeon_emit(&parent->base, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
+ radeon_emit(&parent->base, PKT3(PKT3_INDIRECT_BUFFER, 2, 0));
radeon_emit(&parent->base, child->ib.ib_mc_address);
radeon_emit(&parent->base, child->ib.ib_mc_address >> 32);
radeon_emit(&parent->base, child->ib.size);
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
index 8ecd79df109..8916002cad4 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
@@ -1148,7 +1148,7 @@ static bool amdgpu_cs_check_space(struct radeon_cmdbuf *rcs, unsigned dw)
while ((rcs->current.cdw & ib_pad_dw_mask) != ib_pad_dw_mask - 3)
radeon_emit(rcs, PKT3_NOP_PAD);
- radeon_emit(rcs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
+ radeon_emit(rcs, PKT3(PKT3_INDIRECT_BUFFER, 2, 0));
radeon_emit(rcs, va);
radeon_emit(rcs, va >> 32);
uint32_t *new_ptr_ib_size = &rcs->current.buf[rcs->current.cdw++];
--
cgit v1.2.1

69
debian/patches/0006_radv:_Simplify_IB2_workaround..patch vendored
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@ -1,69 +0,0 @@
From d16d9ef34550da313bbb45e5782136d6bb3b5964 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Timur=20Krist=C3=B3f?= <timur.kristof@gmail.com>
Date: Mon, 17 Apr 2023 16:13:16 +0200
Subject: radv: Simplify IB2 workaround.
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Move compute IB2 check to the winsys, because IB2 only works on
GFX queues and not any other queue types.
Then, simplify the workaround condition in the cmd buffer.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Tatsuyuki Ishi <ishitatsuyuki@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22533>
---
src/amd/vulkan/radv_cmd_buffer.c | 19 ++++++-------------
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c | 2 +-
2 files changed, 7 insertions(+), 14 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 5cc066e7e65..6de52df3ef7 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -7503,20 +7503,13 @@ radv_CmdExecuteCommands(VkCommandBuffer commandBuffer, uint32_t commandBufferCou
for (uint32_t i = 0; i < commandBufferCount; i++) {
RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
- bool allow_ib2 = true;
- if (secondary->device->physical_device->rad_info.gfx_level <= GFX7 &&
- secondary->state.uses_draw_indirect_multi) {
- /* Do not launch an IB2 for secondary command buffers that contain
- * DRAW_{INDEX}_INDIRECT_MULTI on GFX7 because it's illegal and hang the GPU.
- */
- allow_ib2 = false;
- }
-
- if (secondary->qf == RADV_QUEUE_COMPUTE) {
- /* IB2 packets are not supported on compute queues according to PAL. */
- allow_ib2 = false;
- }
+ /* Do not launch an IB2 for secondary command buffers that contain
+ * DRAW_{INDEX}_INDIRECT_MULTI on GFX7 because it's illegal and hang the GPU.
+ */
+ const bool allow_ib2 =
+ !secondary->state.uses_draw_indirect_multi ||
+ secondary->device->physical_device->rad_info.gfx_level >= GFX8;
primary->scratch_size_per_wave_needed =
MAX2(primary->scratch_size_per_wave_needed, secondary->scratch_size_per_wave_needed);
diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
index 1b007557571..ee2108bc4a4 100644
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
@@ -648,7 +648,7 @@ radv_amdgpu_cs_execute_secondary(struct radeon_cmdbuf *_parent, struct radeon_cm
struct radv_amdgpu_cs *parent = radv_amdgpu_cs(_parent);
struct radv_amdgpu_cs *child = radv_amdgpu_cs(_child);
struct radv_amdgpu_winsys *ws = parent->ws;
- bool use_ib2 = parent->use_ib && allow_ib2;
+ const bool use_ib2 = parent->use_ib && allow_ib2 && parent->hw_ip == AMD_IP_GFX;
if (parent->status != VK_SUCCESS || child->status != VK_SUCCESS)
return;
--
cgit v1.2.1

34
debian/patches/0007_radv:_Remove_IB2_workaround_from_mesh_shader_draws..patch vendored
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@ -1,34 +0,0 @@
From 46a14390d8bcb7e91620f94f9d7bde2dc449190d Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Timur=20Krist=C3=B3f?= <timur.kristof@gmail.com>
Date: Tue, 18 Apr 2023 12:56:04 +0200
Subject: radv: Remove IB2 workaround from mesh shader draws.
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
The GPUs which need the workaround do not support mesh shaders.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Tatsuyuki Ishi <ishitatsuyuki@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22533>
---
src/amd/vulkan/radv_cmd_buffer.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 6de52df3ef7..e85e1fd9544 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -8115,8 +8115,6 @@ radv_cs_emit_indirect_mesh_draw_packet(struct radv_cmd_buffer *cmd_buffer, uint3
radeon_emit(cs, count_va >> 32);
radeon_emit(cs, stride);
radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX);
-
- cmd_buffer->state.uses_draw_indirect_multi = true;
}
ALWAYS_INLINE static void
--
cgit v1.2.1

67
debian/patches/0008_radv:_Enable_IB2_workaround_on_all_indirect_draws..patch vendored
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@ -1,67 +0,0 @@
From acce5c3fe1fa2930adb6cdc152f3c371b1d24290 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Timur=20Krist=C3=B3f?= <timur.kristof@gmail.com>
Date: Tue, 18 Apr 2023 12:59:33 +0200
Subject: radv: Enable IB2 workaround on all indirect draws.
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
IB2 packets hang GFX6 when they contain any indirect draws,
not just the MULTI versions.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Tatsuyuki Ishi <ishitatsuyuki@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22533>
---
src/amd/vulkan/radv_cmd_buffer.c | 8 ++++----
src/amd/vulkan/radv_private.h | 4 ++--
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index e85e1fd9544..541454c8f2d 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -7505,10 +7505,10 @@ radv_CmdExecuteCommands(VkCommandBuffer commandBuffer, uint32_t commandBufferCou
RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
/* Do not launch an IB2 for secondary command buffers that contain
- * DRAW_{INDEX}_INDIRECT_MULTI on GFX7 because it's illegal and hang the GPU.
+ * DRAW_{INDEX}_INDIRECT_{MULTI} on GFX6-7 because it's illegal and hangs the GPU.
*/
const bool allow_ib2 =
- !secondary->state.uses_draw_indirect_multi ||
+ !secondary->state.uses_draw_indirect ||
secondary->device->physical_device->rad_info.gfx_level >= GFX8;
primary->scratch_size_per_wave_needed =
@@ -8073,9 +8073,9 @@ radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer, bool index
radeon_emit(cs, count_va >> 32);
radeon_emit(cs, stride); /* stride */
radeon_emit(cs, di_src_sel);
-
- cmd_buffer->state.uses_draw_indirect_multi = true;
}
+
+ cmd_buffer->state.uses_draw_indirect = true;
}
ALWAYS_INLINE static void
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index f0fea917c91..981d6694254 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1657,8 +1657,8 @@ struct radv_cmd_state {
uint8_t cb_mip[MAX_RTS];
- /* Whether DRAW_{INDEX}_INDIRECT_MULTI is emitted. */
- bool uses_draw_indirect_multi;
+ /* Whether DRAW_{INDEX}_INDIRECT_{MULTI} is emitted. */
+ bool uses_draw_indirect;
uint32_t rt_stack_size;
--
cgit v1.2.1

94
debian/patches/0009_anv:_override_vendorID_for_Cyberpunk_2077.patch vendored
View File

@ -1,94 +0,0 @@
From 5731ebac404a142fb1c1d1f0755d22beed40528a Mon Sep 17 00:00:00 2001
From: Felix DeGrood <felix.j.degrood@intel.com>
Date: Mon, 15 May 2023 22:44:45 +0000
Subject: anv: override vendorID for Cyberpunk 2077
A recent update to Cyberpunk 2077 enables XeSS code for Intel GPUs
which is causing the game to crash in the XeSS libraries. As a
temporary work around, stop identifying as Intel for Cyberpunk so
XeSS falls back to the cross-vendor path.
References: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8860
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23271>
---
src/intel/vulkan/anv_device.c | 5 +++++
src/intel/vulkan/anv_private.h | 1 +
src/util/00-mesa-defaults.conf | 3 +++
src/util/driconf.h | 3 +++
4 files changed, 12 insertions(+)
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 44a591531c0..da9e05b9ced 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -85,6 +85,7 @@ static const driOptionDescription anv_dri_options[] = {
DRI_CONF_VK_WSI_FORCE_BGRA8_UNORM_FIRST(false)
DRI_CONF_LIMIT_TRIG_INPUT_RANGE(false)
DRI_CONF_ANV_MESH_CONV_PRIM_ATTRS_TO_VERT_ATTRS(-2)
+ DRI_CONF_FORCE_VK_VENDOR(0)
DRI_CONF_SECTION_END
DRI_CONF_SECTION_QUALITY
@@ -1500,6 +1501,8 @@ anv_init_dri_options(struct anv_instance *instance)
driQueryOptioni(&instance->dri_options, "generated_indirect_threshold");
instance->query_clear_with_blorp_threshold =
driQueryOptioni(&instance->dri_options, "query_clear_with_blorp_threshold");
+ instance->force_vk_vendor =
+ driQueryOptioni(&instance->dri_options, "force_vk_vendor");
}
VkResult anv_CreateInstance(
@@ -1749,6 +1752,8 @@ void anv_GetPhysicalDeviceProperties(
.sparseProperties = {0}, /* Broadwell doesn't do sparse. */
};
+ if (unlikely(pdevice->instance->force_vk_vendor))
+ pProperties->vendorID = pdevice->instance->force_vk_vendor;
snprintf(pProperties->deviceName, sizeof(pProperties->deviceName),
"%s", pdevice->info.name);
memcpy(pProperties->pipelineCacheUUID,
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index 8c4099e3b7b..b6401c44782 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -1037,6 +1037,7 @@ struct anv_instance {
float lower_depth_range_rate;
unsigned generated_indirect_threshold;
unsigned query_clear_with_blorp_threshold;
+ unsigned force_vk_vendor;
/* HW workarounds */
bool no_16bit;
diff --git a/src/util/00-mesa-defaults.conf b/src/util/00-mesa-defaults.conf
index b5f8b233a7d..a58831bc304 100644
--- a/src/util/00-mesa-defaults.conf
+++ b/src/util/00-mesa-defaults.conf
@@ -1056,6 +1056,9 @@ TODO: document the other workarounds.
<application name="NieR:Automata" executable="NieRAutomata.exe">
<option name="limit_trig_input_range" value="true" />
</application>
+ <application name="Cyberpunk 2077" executable="Cyberpunk2077.exe">
+ <option name="force_vk_vendor" value="-1" />
+ </application>
<!--
Disable 16-bit feature on zink and angle so that GLES mediump doesn't
lower to our inefficent 16-bit shader support. No need to do so for
diff --git a/src/util/driconf.h b/src/util/driconf.h
index ac51622830d..108cc017c43 100644
--- a/src/util/driconf.h
+++ b/src/util/driconf.h
@@ -310,6 +310,9 @@
DRI_CONF_OPT_B(ignore_discard_framebuffer, def, \
"Ignore glDiscardFramebuffer/glInvalidateFramebuffer, workaround for games that use it incorrectly")
+#define DRI_CONF_FORCE_VK_VENDOR(def) \
+ DRI_CONF_OPT_I(force_vk_vendor, 0, -1, 2147483647, "Override GPU vendor id")
+
/**
* \brief Image quality-related options
*/
--
cgit v1.2.1

39
debian/patches/0010_util_driconf:_pin_minImageCount_to_three_for_Path_of_Exile.patch vendored
View File

@ -1,39 +0,0 @@
From cb41ef0d3f537f8d1fb345cf5bdcc30070333c8b Mon Sep 17 00:00:00 2001
From: Gert Wollny <gert.wollny@collabora.com>
Date: Mon, 27 Feb 2023 09:56:41 +0100
Subject: util/driconf: pin minImageCount to three for "Path of Exile"
"Path of Exile" will fail with an error "unsupported backbuffer image count"
when vkGetPhysicalDeviceSurfaceCapabilitiesKHR reports more than 3 as
minImageCount.
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21547>
---
src/util/00-mesa-defaults.conf | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/src/util/00-mesa-defaults.conf b/src/util/00-mesa-defaults.conf
index 554115cedfc..843beae6609 100644
--- a/src/util/00-mesa-defaults.conf
+++ b/src/util/00-mesa-defaults.conf
@@ -891,6 +891,16 @@ TODO: document the other workarounds.
<!-- https://gitlab.freedesktop.org/mesa/mesa/-/issues/5437 -->
<option name="vk_dont_care_as_load" value="true" />
</application>
+
+ <!-- Path of Exile stops with "unsupported backbuffer count" when more than
+ 3 swapchain image are reported. -->
+ <application name="Path of Exile" executable="PathOfExile_x64Steam.exe">
+ <option name="vk_x11_override_min_image_count" value="3" />
+ </application>
+ <application name="Path of Exile" executable="PathOfExileSteam.exe">
+ <option name="vk_x11_override_min_image_count" value="3" />
+ </application>
+
</device>
<!-- vmwgfx doesn't like full buffer swaps and can't sync to vertical retraces.-->
<device driver="vmwgfx">
--
cgit v1.2.1

15
debian/patches/series vendored
View File

@ -1,15 +0,0 @@
07_gallium-fix-build-failure-on-powerpcspe.diff
path_max.diff
src_glx_dri_common.h.diff
#kisak-mesa PPA Backports:
0001_radv_amdgpu:_Remove_unnecessary_assertions_from_chaining..patch
0002_radv:_Disallow_IB2_on_GFX6_when_using_draw_indirect_multi..patch
0003_radv:_Use_IB_BOs_(chaining)_by_default_on_GFX6..patch
0004_radv:_Chain_command_buffers_on_GFX6_in_radv_queue..patch
0005_amd:_Rename_INDIRECT_BUFFER_CIK_to_just_INDIRECT_BUFFER..patch
0006_radv:_Simplify_IB2_workaround..patch
0007_radv:_Remove_IB2_workaround_from_mesh_shader_draws..patch
0008_radv:_Enable_IB2_workaround_on_all_indirect_draws..patch
0009_anv:_override_vendorID_for_Cyberpunk_2077.patch
0010_util_driconf:_pin_minImageCount_to_three_for_Path_of_Exile.patch

0
debian/patches/07_gallium-fix-build-failure-on-powerpcspe.diff → patches/07_gallium-fix-build-failure-on-powerpcspe.diff
View File

0
debian/patches/path_max.diff → patches/path_max.diff
View File

153
patches/revert-af1ee8e01044.diff Normal file
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@ -0,0 +1,153 @@
From 0c3587a2f8e1b6cfadf9a4bbb6ae4b2c3e14a651 Mon Sep 17 00:00:00 2001
From: Leandro Ribeiro <leandro.ribeiro@collabora.com>
Date: Sun, 10 Apr 2022 22:54:36 -0300
Subject: [PATCH] Revert "egl/wayland: deprecate drm_handle_format() and
drm_handle_capabilities()"
Commit af1ee8e010441f8f2ed8c77065b159652a4ac9fe dropped support to
wl_drm, as we thought that most compositors from active projects were
already supporting zwp_linux_dmabuf_v1.
But that's not true, so revert this commit in order to give these
projects a longer transition period.
Note that we didn't add back the support to GEM name API, and that was
on purpose.
Signed-off-by: Leandro Ribeiro <leandro.ribeiro@collabora.com>
---
src/egl/drivers/dri2/egl_dri2.h | 1 +
src/egl/drivers/dri2/platform_wayland.c | 59 +++++++++++++++++++------
2 files changed, 47 insertions(+), 13 deletions(-)
diff --git a/src/egl/drivers/dri2/egl_dri2.h b/src/egl/drivers/dri2/egl_dri2.h
index 89158993efdd..1c840a966b3c 100644
--- a/src/egl/drivers/dri2/egl_dri2.h
+++ b/src/egl/drivers/dri2/egl_dri2.h
@@ -284,6 +284,7 @@ struct dri2_egl_display
struct zwp_linux_dmabuf_feedback_v1 *wl_dmabuf_feedback;
struct dmabuf_feedback_format_table format_table;
bool authenticated;
+ uint32_t capabilities;
char *device_name;
#endif
diff --git a/src/egl/drivers/dri2/platform_wayland.c b/src/egl/drivers/dri2/platform_wayland.c
index e9ecf6d1e716..19fad8bfa08e 100644
--- a/src/egl/drivers/dri2/platform_wayland.c
+++ b/src/egl/drivers/dri2/platform_wayland.c
@@ -1344,7 +1344,7 @@ create_wl_buffer(struct dri2_egl_display *dri2_dpy,
struct dri2_egl_surface *dri2_surf,
__DRIimage *image)
{
- struct wl_buffer *ret;
+ struct wl_buffer *ret = NULL;
EGLBoolean query;
int width, height, fourcc, num_planes;
uint64_t modifier = DRM_FORMAT_MOD_INVALID;
@@ -1448,11 +1448,28 @@ create_wl_buffer(struct dri2_egl_display *dri2_dpy,
ret = zwp_linux_buffer_params_v1_create_immed(params, width, height,
fourcc, 0);
zwp_linux_buffer_params_v1_destroy(params);
+ } else {
+ struct wl_drm *wl_drm =
+ dri2_surf ? dri2_surf->wl_drm_wrapper : dri2_dpy->wl_drm;
+ int fd, stride;
+
+ if (num_planes > 1)
+ return NULL;
+
+ query = dri2_dpy->image->queryImage(image, __DRI_IMAGE_ATTRIB_FD, &fd);
+ query &= dri2_dpy->image->queryImage(image, __DRI_IMAGE_ATTRIB_STRIDE, &stride);
+ if (!query) {
+ if (fd >= 0)
+ close(fd);
+ return NULL;
+ }
- return ret;
+ ret = wl_drm_create_prime_buffer(wl_drm, fd, width, height, fourcc, 0,
+ stride, 0, 0, 0, 0);
+ close(fd);
}
- return NULL;
+ return ret;
}
static EGLBoolean
@@ -1699,16 +1716,21 @@ drm_handle_device(void *data, struct wl_drm *drm, const char *device)
static void
drm_handle_format(void *data, struct wl_drm *drm, uint32_t format)
{
- /* deprecated, as compositors already support the dma-buf protocol extension
- * and so we can rely on dmabuf_handle_modifier() to receive formats and
- * modifiers */
+ struct dri2_egl_display *dri2_dpy = data;
+ int visual_idx = dri2_wl_visual_idx_from_fourcc(format);
+
+ if (visual_idx == -1)
+ return;
+
+ BITSET_SET(dri2_dpy->formats.formats_bitmap, visual_idx);
}
static void
drm_handle_capabilities(void *data, struct wl_drm *drm, uint32_t value)
{
- /* deprecated, as compositors already support the dma-buf protocol extension
- * and so we can rely on it to create wl_buffer's */
+ struct dri2_egl_display *dri2_dpy = data;
+
+ dri2_dpy->capabilities = value;
}
static void
@@ -2077,13 +2099,12 @@ dri2_initialize_wayland_drm(_EGLDisplay *disp)
wl_registry_add_listener(dri2_dpy->wl_registry,
&registry_listener_drm, dri2_dpy);
- /* The compositor must expose the dma-buf interface. */
- if (roundtrip(dri2_dpy) < 0 || dri2_dpy->wl_dmabuf == NULL)
+ if (roundtrip(dri2_dpy) < 0)
goto cleanup;
/* Get default dma-buf feedback */
- if (zwp_linux_dmabuf_v1_get_version(dri2_dpy->wl_dmabuf) >=
- ZWP_LINUX_DMABUF_V1_GET_DEFAULT_FEEDBACK_SINCE_VERSION) {
+ if (dri2_dpy->wl_dmabuf && zwp_linux_dmabuf_v1_get_version(dri2_dpy->wl_dmabuf) >=
+ ZWP_LINUX_DMABUF_V1_GET_DEFAULT_FEEDBACK_SINCE_VERSION) {
dmabuf_feedback_format_table_init(&dri2_dpy->format_table);
dri2_dpy->wl_dmabuf_feedback =
zwp_linux_dmabuf_v1_get_default_feedback(dri2_dpy->wl_dmabuf);
@@ -2091,7 +2112,6 @@ dri2_initialize_wayland_drm(_EGLDisplay *disp)
&dmabuf_feedback_listener, dri2_dpy);
}
- /* Receive events from the interfaces */
if (roundtrip(dri2_dpy) < 0)
goto cleanup;
@@ -2178,6 +2198,19 @@ dri2_initialize_wayland_drm(_EGLDisplay *disp)
dri2_wl_setup_swap_interval(disp);
+ if (dri2_dpy->wl_drm) {
+ /* To use Prime, we must have _DRI_IMAGE v7 at least. createImageFromFds
+ * support indicates that Prime export/import is supported by the driver.
+ * We deprecated the support to GEM names API, so we bail out if the
+ * driver does not suport Prime. */
+ if (!(dri2_dpy->capabilities & WL_DRM_CAPABILITY_PRIME) ||
+ (dri2_dpy->image->base.version < 7) ||
+ (dri2_dpy->image->createImageFromFds == NULL)) {
+ _eglLog(_EGL_WARNING, "wayland-egl: display does not support prime");
+ goto cleanup;
+ }
+ }
+
if (dri2_dpy->is_different_gpu &&
(dri2_dpy->image->base.version < 9 ||
dri2_dpy->image->blitImage == NULL)) {
--
GitLab

0
debian/patches/src_glx_dri_common.h.diff → patches/src_glx_dri_common.h.diff
View File