diff --git a/patches/0001-cachyos-base-all.patch b/patches/0001-cachyos-base-all.patch index 4b519e9..8b2a3d1 100644 --- a/patches/0001-cachyos-base-all.patch +++ b/patches/0001-cachyos-base-all.patch @@ -1,4 +1,4 @@ -From 388846a7197e09827139dd2e32554cf564cee8d7 Mon Sep 17 00:00:00 2001 +From e2e1bb55424f35d93c9110d4f1f1787999f1cd34 Mon Sep 17 00:00:00 2001 From: Peter Jung Date: Fri, 8 Nov 2024 16:53:48 +0100 Subject: [PATCH 01/13] address-masking @@ -57,7 +57,7 @@ index 39c7cf82b0c2..43844510d5d0 100644 -- 2.47.0 -From 540411a33c5579d41cde12dba682c174197a958c Mon Sep 17 00:00:00 2001 +From af2c10989d40a789c13a4cea89174587a6c85cc6 Mon Sep 17 00:00:00 2001 From: Peter Jung Date: Fri, 8 Nov 2024 16:54:07 +0100 Subject: [PATCH 02/13] amd-cache-optimizer @@ -350,7 +350,7 @@ index 000000000000..679613d02b9a -- 2.47.0 -From cc249b74bd76342d380a67f5ba39401d42bfd99b Mon Sep 17 00:00:00 2001 +From ee21687468f304e9fbf16b13d4dbf54684a42928 Mon Sep 17 00:00:00 2001 From: Peter Jung Date: Fri, 8 Nov 2024 16:54:24 +0100 Subject: [PATCH 03/13] amd-pstate @@ -1612,7 +1612,7 @@ index dd4682857c12..23698d0f4bb4 100644 -- 2.47.0 -From c22fef0041e87b7577f076e2a524b295ae0d3195 Mon Sep 17 00:00:00 2001 +From 0da4917ae42888bccbf6fabd6102d994d34262da Mon Sep 17 00:00:00 2001 From: Peter Jung Date: Fri, 8 Nov 2024 16:55:11 +0100 Subject: [PATCH 04/13] bbr3 @@ -4998,7 +4998,7 @@ index 4d40615dc8fc..f27941201ef2 100644 -- 2.47.0 -From 13131fcbfd0af9c911cf7cf7623652a6123aeee0 Mon Sep 17 00:00:00 2001 +From 70a49c61f77983ee2e92bfd25e18386fc982d158 Mon Sep 17 00:00:00 2001 From: Peter Jung Date: Fri, 8 Nov 2024 16:56:22 +0100 Subject: [PATCH 05/13] cachy @@ -5097,7 +5097,7 @@ index be010fec7654..900113802ffc 100644 Safety option to keep boot IRQs enabled. This should never be necessary. diff --git a/Makefile b/Makefile -index 692bbdf40fb5..c89daa69f457 100644 +index b8641dde171f..b6d641c53e15 100644 --- a/Makefile +++ b/Makefile @@ -803,11 +803,19 @@ KBUILD_CFLAGS += -fno-delete-null-pointer-checks @@ -6037,7 +6037,7 @@ index df17e79c45c7..e454488c1a31 100644 + endmenu diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c -index 4f19e9736a67..575fdcfb138c 100644 +index 245a26cdfc52..d6a6ac0b32b2 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -4445,7 +4445,7 @@ static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) @@ -6139,10 +6139,10 @@ index d5d6ab484e5a..dccba7bcdf97 100644 } diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c -index 80e60ea2d11e..51dea35848f6 100644 +index ee1bcfaae3e3..3388604f222b 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c -@@ -2775,7 +2775,10 @@ int smu_get_power_limit(void *handle, +@@ -2785,7 +2785,10 @@ int smu_get_power_limit(void *handle, *limit = smu->max_power_limit; break; case SMU_PPT_LIMIT_MIN: @@ -6154,7 +6154,7 @@ index 80e60ea2d11e..51dea35848f6 100644 break; default: return -EINVAL; -@@ -2799,7 +2802,14 @@ static int smu_set_power_limit(void *handle, uint32_t limit) +@@ -2809,7 +2812,14 @@ static int smu_set_power_limit(void *handle, uint32_t limit) if (smu->ppt_funcs->set_power_limit) return smu->ppt_funcs->set_power_limit(smu, limit_type, limit); @@ -10656,10 +10656,10 @@ index d9c7edb6422b..b57c72793580 100644 void page_cache_ra_unbounded(struct readahead_control *, unsigned long nr_to_read, unsigned long lookahead_count); diff --git a/include/linux/user_namespace.h b/include/linux/user_namespace.h -index 6030a8235617..60b7fe5fa74a 100644 +index 0327031865c6..0ab9fc3bc485 100644 --- a/include/linux/user_namespace.h +++ b/include/linux/user_namespace.h -@@ -156,6 +156,8 @@ static inline void set_userns_rlimit_max(struct user_namespace *ns, +@@ -157,6 +157,8 @@ static inline void set_userns_rlimit_max(struct user_namespace *ns, #ifdef CONFIG_USER_NS @@ -10668,7 +10668,7 @@ index 6030a8235617..60b7fe5fa74a 100644 static inline struct user_namespace *get_user_ns(struct user_namespace *ns) { if (ns) -@@ -189,6 +191,8 @@ extern bool current_in_userns(const struct user_namespace *target_ns); +@@ -190,6 +192,8 @@ extern bool current_in_userns(const struct user_namespace *target_ns); struct ns_common *ns_get_owner(struct ns_common *ns); #else @@ -11049,7 +11049,7 @@ index 4430ac68e4c4..3bd08b60a9b3 100644 EXPORT_SYMBOL_GPL(dirty_writeback_interval); diff --git a/mm/page_alloc.c b/mm/page_alloc.c -index ec459522c293..e0f083a5b7d3 100644 +index f9111356d104..4dd6fdecaede 100644 --- a/mm/page_alloc.c +++ b/mm/page_alloc.c @@ -271,7 +271,11 @@ const char * const migratetype_names[MIGRATE_TYPES] = { @@ -11065,7 +11065,7 @@ index ec459522c293..e0f083a5b7d3 100644 /* movable_zone is the "real" zone pages in ZONE_MOVABLE are taken from */ diff --git a/mm/swap.c b/mm/swap.c -index 9caf6b017cf0..00c1307f3874 100644 +index 1e734a5a6453..9dc25512cc78 100644 --- a/mm/swap.c +++ b/mm/swap.c @@ -1126,6 +1126,10 @@ void folio_batch_remove_exceptionals(struct folio_batch *fbatch) @@ -11102,7 +11102,7 @@ index bd5183dfd879..3a410f53a07c 100644 /* diff --git a/mm/vmscan.c b/mm/vmscan.c -index f5bcd08527ae..83c66d0267c0 100644 +index b7f326f87363..ac53e21d28e7 100644 --- a/mm/vmscan.c +++ b/mm/vmscan.c @@ -200,7 +200,11 @@ struct scan_control { @@ -11263,20 +11263,32 @@ index 663ce300dd06..f83493838cf9 100644 -- 2.47.0 -From 9cb83850dc8662524d629fc34e92b3bfcc50183a Mon Sep 17 00:00:00 2001 +From 2cee36cd0b5c8545ff7c8993cfeb5a8765f3143c Mon Sep 17 00:00:00 2001 From: Peter Jung -Date: Fri, 8 Nov 2024 17:43:05 +0100 +Date: Thu, 14 Nov 2024 17:04:45 +0100 Subject: [PATCH 06/13] fixes Signed-off-by: Peter Jung --- - arch/Kconfig | 4 +- - arch/x86/kernel/cpu/amd.c | 11 +++++ - drivers/bluetooth/btusb.c | 4 ++ - drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 5 ++ - .../drm/amd/display/dc/bios/bios_parser2.c | 4 +- - drivers/gpu/drm/drm_edid.c | 47 +++++++++++++++++-- - 6 files changed, 69 insertions(+), 6 deletions(-) + arch/Kconfig | 4 +- + arch/x86/kernel/cpu/amd.c | 11 ++ + drivers/bluetooth/btusb.c | 4 + + drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 5 + + .../drm/amd/display/dc/bios/bios_parser2.c | 2 +- + drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 108 ++++++------------ + drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 11 +- + .../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 20 ++-- + .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 20 ++-- + .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 21 ++-- + .../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 17 +-- + .../gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c | 17 +-- + .../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 33 +++--- + .../drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 21 ++-- + .../drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c | 23 ++-- + drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 8 -- + drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h | 2 - + drivers/gpu/drm/drm_edid.c | 47 +++++++- + 18 files changed, 198 insertions(+), 176 deletions(-) diff --git a/arch/Kconfig b/arch/Kconfig index 975dd22a2dbd..de69b8f5b5be 100644 @@ -11354,20 +11366,731 @@ index 9c3b7b027485..ad5c05ee92f3 100644 return pci_register_driver(&amdgpu_kms_pci_driver); diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c -index 0d8498ab9b23..be8fbb04ad98 100644 +index be8fbb04ad98..902491669cbc 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c +++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c -@@ -3127,7 +3127,9 @@ static enum bp_result bios_parser_get_vram_info( +@@ -3122,7 +3122,7 @@ static enum bp_result bios_parser_get_vram_info( + struct dc_vram_info *info) + { + struct bios_parser *bp = BP_FROM_DCB(dcb); +- static enum bp_result result = BP_RESULT_BADBIOSTABLE; ++ enum bp_result result = BP_RESULT_BADBIOSTABLE; + struct atom_common_table_header *header; struct atom_data_revision revision; - // vram info moved to umc_info for DCN4x -- if (info && DATA_TABLES(umc_info)) { -+ if (dcb->ctx->dce_version >= DCN_VERSION_4_01 && -+ dcb->ctx->dce_version < DCN_VERSION_MAX && -+ info && DATA_TABLES(umc_info)) { - header = GET_IMAGE(struct atom_common_table_header, - DATA_TABLES(umc_info)); +diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +index 3388604f222b..daa870302cc3 100644 +--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +@@ -1257,42 +1257,18 @@ static int smu_sw_init(void *handle) + INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn); + atomic64_set(&smu->throttle_int_counter, 0); + smu->watermarks_bitmap = 0; +- smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; +- smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; +- smu->user_dpm_profile.user_workload_mask = 0; + atomic_set(&smu->smu_power.power_gate.vcn_gated, 1); + atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1); + atomic_set(&smu->smu_power.power_gate.vpe_gated, 1); + atomic_set(&smu->smu_power.power_gate.umsch_mm_gated, 1); + +- smu->workload_priority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0; +- smu->workload_priority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1; +- smu->workload_priority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2; +- smu->workload_priority[PP_SMC_POWER_PROFILE_VIDEO] = 3; +- smu->workload_priority[PP_SMC_POWER_PROFILE_VR] = 4; +- smu->workload_priority[PP_SMC_POWER_PROFILE_COMPUTE] = 5; +- smu->workload_priority[PP_SMC_POWER_PROFILE_CUSTOM] = 6; +- + if (smu->is_apu || +- !smu_is_workload_profile_available(smu, PP_SMC_POWER_PROFILE_FULLSCREEN3D)) { +- smu->driver_workload_mask = +- 1 << smu->workload_priority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT]; +- } else { +- smu->driver_workload_mask = +- 1 << smu->workload_priority[PP_SMC_POWER_PROFILE_FULLSCREEN3D]; +- smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_FULLSCREEN3D; +- } +- +- smu->workload_mask = smu->driver_workload_mask | +- smu->user_dpm_profile.user_workload_mask; +- smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; +- smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D; +- smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING; +- smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO; +- smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR; +- smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE; +- smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM; ++ !smu_is_workload_profile_available(smu, PP_SMC_POWER_PROFILE_FULLSCREEN3D)) ++ smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; ++ else ++ smu->power_profile_mode = PP_SMC_POWER_PROFILE_FULLSCREEN3D; ++ + smu->display_config = &adev->pm.pm_display_cfg; + + smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; +@@ -2232,24 +2208,23 @@ static int smu_enable_umd_pstate(void *handle, + } + + static int smu_bump_power_profile_mode(struct smu_context *smu, +- long *param, +- uint32_t param_size) ++ long *param, ++ uint32_t param_size, ++ bool enable) + { + int ret = 0; + + if (smu->ppt_funcs->set_power_profile_mode) +- ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size); ++ ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size, enable); + + return ret; + } + + static int smu_adjust_power_state_dynamic(struct smu_context *smu, + enum amd_dpm_forced_level level, +- bool skip_display_settings, +- bool init) ++ bool skip_display_settings) + { + int ret = 0; +- int index = 0; + long workload[1]; + struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); + +@@ -2287,13 +2262,10 @@ static int smu_adjust_power_state_dynamic(struct smu_context *smu, + } + + if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && +- smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { +- index = fls(smu->workload_mask); +- index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; +- workload[0] = smu->workload_setting[index]; ++ smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { ++ workload[0] = smu->power_profile_mode; + +- if (init || smu->power_profile_mode != workload[0]) +- smu_bump_power_profile_mode(smu, workload, 0); ++ smu_bump_power_profile_mode(smu, workload, 0, true); + } + + return ret; +@@ -2313,13 +2285,13 @@ static int smu_handle_task(struct smu_context *smu, + ret = smu_pre_display_config_changed(smu); + if (ret) + return ret; +- ret = smu_adjust_power_state_dynamic(smu, level, false, false); ++ ret = smu_adjust_power_state_dynamic(smu, level, false); + break; + case AMD_PP_TASK_COMPLETE_INIT: +- ret = smu_adjust_power_state_dynamic(smu, level, true, true); ++ ret = smu_adjust_power_state_dynamic(smu, level, true); + break; + case AMD_PP_TASK_READJUST_POWER_STATE: +- ret = smu_adjust_power_state_dynamic(smu, level, true, false); ++ ret = smu_adjust_power_state_dynamic(smu, level, true); + break; + default: + break; +@@ -2341,12 +2313,11 @@ static int smu_handle_dpm_task(void *handle, + + static int smu_switch_power_profile(void *handle, + enum PP_SMC_POWER_PROFILE type, +- bool en) ++ bool enable) + { + struct smu_context *smu = handle; + struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); + long workload[1]; +- uint32_t index; + + if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) + return -EOPNOTSUPP; +@@ -2354,24 +2325,15 @@ static int smu_switch_power_profile(void *handle, + if (!(type < PP_SMC_POWER_PROFILE_CUSTOM)) + return -EINVAL; + +- if (!en) { +- smu->driver_workload_mask &= ~(1 << smu->workload_priority[type]); +- index = fls(smu->workload_mask); +- index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; +- workload[0] = smu->workload_setting[index]; +- } else { +- smu->driver_workload_mask |= (1 << smu->workload_priority[type]); +- index = fls(smu->workload_mask); +- index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; +- workload[0] = smu->workload_setting[index]; +- } ++ /* don't disable the user's preference */ ++ if (!enable && type == smu->power_profile_mode) ++ return 0; + +- smu->workload_mask = smu->driver_workload_mask | +- smu->user_dpm_profile.user_workload_mask; ++ workload[0] = type; + + if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && +- smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) +- smu_bump_power_profile_mode(smu, workload, 0); ++ smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) ++ smu_bump_power_profile_mode(smu, workload, 0, enable); + + return 0; + } +@@ -3069,21 +3031,25 @@ static int smu_set_power_profile_mode(void *handle, + uint32_t param_size) + { + struct smu_context *smu = handle; +- int ret; ++ long workload[1]; ++ int ret = 0; + + if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || + !smu->ppt_funcs->set_power_profile_mode) + return -EOPNOTSUPP; + +- if (smu->user_dpm_profile.user_workload_mask & +- (1 << smu->workload_priority[param[param_size]])) +- return 0; +- +- smu->user_dpm_profile.user_workload_mask = +- (1 << smu->workload_priority[param[param_size]]); +- smu->workload_mask = smu->user_dpm_profile.user_workload_mask | +- smu->driver_workload_mask; +- ret = smu_bump_power_profile_mode(smu, param, param_size); ++ if (param[param_size] != smu->power_profile_mode) { ++ /* clear the old user preference */ ++ workload[0] = smu->power_profile_mode; ++ ret = smu_bump_power_profile_mode(smu, workload, 0, false); ++ if (ret) ++ return ret; ++ /* set the new user preference */ ++ ret = smu_bump_power_profile_mode(smu, param, param_size, true); ++ if (!ret) ++ /* store the user's preference */ ++ smu->power_profile_mode = param[param_size]; ++ } + + return ret; + } +diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h +index d60d9a12a47e..fc54b2c6ede8 100644 +--- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h ++++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h +@@ -240,7 +240,6 @@ struct smu_user_dpm_profile { + /* user clock state information */ + uint32_t clk_mask[SMU_CLK_COUNT]; + uint32_t clk_dependency; +- uint32_t user_workload_mask; + }; + + #define SMU_TABLE_INIT(tables, table_id, s, a, d) \ +@@ -557,12 +556,10 @@ struct smu_context { + uint32_t hard_min_uclk_req_from_dal; + bool disable_uclk_switch; + ++ /* backend specific workload mask */ + uint32_t workload_mask; +- uint32_t driver_workload_mask; +- uint32_t workload_priority[WORKLOAD_POLICY_MAX]; +- uint32_t workload_setting[WORKLOAD_POLICY_MAX]; ++ /* default/user workload preference */ + uint32_t power_profile_mode; +- uint32_t default_power_profile_mode; + bool pm_enabled; + bool is_apu; + +@@ -734,8 +731,10 @@ struct pptable_funcs { + * create/set custom power profile modes. + * &input: Power profile mode parameters. + * &size: Size of &input. ++ * &enable: enable/disable the profile + */ +- int (*set_power_profile_mode)(struct smu_context *smu, long *input, uint32_t size); ++ int (*set_power_profile_mode)(struct smu_context *smu, long *input, ++ uint32_t size, bool enable); + + /** + * @dpm_set_vcn_enable: Enable/disable VCN engine dynamic power +diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c +index 31fe512028f4..ac7fbb815644 100644 +--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c +@@ -1443,7 +1443,8 @@ static int arcturus_get_power_profile_mode(struct smu_context *smu, + + static int arcturus_set_power_profile_mode(struct smu_context *smu, + long *input, +- uint32_t size) ++ uint32_t size, ++ bool enable) + { + DpmActivityMonitorCoeffInt_t activity_monitor; + int workload_type = 0; +@@ -1455,8 +1456,9 @@ static int arcturus_set_power_profile_mode(struct smu_context *smu, + return -EINVAL; + } + +- if ((profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) && +- (smu->smc_fw_version >= 0x360d00)) { ++ if (enable && ++ (profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) && ++ (smu->smc_fw_version >= 0x360d00)) { + if (size != 10) + return -EINVAL; + +@@ -1520,18 +1522,18 @@ static int arcturus_set_power_profile_mode(struct smu_context *smu, + return -EINVAL; + } + ++ if (enable) ++ smu->workload_mask |= (1 << workload_type); ++ else ++ smu->workload_mask &= ~(1 << workload_type); + ret = smu_cmn_send_smc_msg_with_param(smu, + SMU_MSG_SetWorkloadMask, + smu->workload_mask, + NULL); +- if (ret) { ++ if (ret) + dev_err(smu->adev->dev, "Fail to set workload type %d\n", workload_type); +- return ret; +- } +- +- smu_cmn_assign_power_profile(smu); + +- return 0; ++ return ret; + } + + static int arcturus_set_performance_level(struct smu_context *smu, +diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c +index bb4ae529ae20..d667bff97a0f 100644 +--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c +@@ -2004,19 +2004,19 @@ static int navi10_get_power_profile_mode(struct smu_context *smu, char *buf) + return size; + } + +-static int navi10_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size) ++static int navi10_set_power_profile_mode(struct smu_context *smu, long *input, ++ uint32_t size, bool enable) + { + DpmActivityMonitorCoeffInt_t activity_monitor; + int workload_type, ret = 0; ++ uint32_t profile_mode = input[size]; + +- smu->power_profile_mode = input[size]; +- +- if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) { +- dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode); ++ if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) { ++ dev_err(smu->adev->dev, "Invalid power profile mode %d\n", profile_mode); + return -EINVAL; + } + +- if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { ++ if (enable && profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { + if (size != 10) + return -EINVAL; + +@@ -2078,16 +2078,18 @@ static int navi10_set_power_profile_mode(struct smu_context *smu, long *input, u + /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ + workload_type = smu_cmn_to_asic_specific_index(smu, + CMN2ASIC_MAPPING_WORKLOAD, +- smu->power_profile_mode); ++ profile_mode); + if (workload_type < 0) + return -EINVAL; + ++ if (enable) ++ smu->workload_mask |= (1 << workload_type); ++ else ++ smu->workload_mask &= ~(1 << workload_type); + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask, + smu->workload_mask, NULL); + if (ret) + dev_err(smu->adev->dev, "[%s] Failed to set work load mask!", __func__); +- else +- smu_cmn_assign_power_profile(smu); + + return ret; + } +diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c +index ca94c52663c0..e04081d95763 100644 +--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c +@@ -1706,22 +1706,23 @@ static int sienna_cichlid_get_power_profile_mode(struct smu_context *smu, char * + return size; + } + +-static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size) ++static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, ++ long *input, uint32_t size, ++ bool enable) + { + + DpmActivityMonitorCoeffIntExternal_t activity_monitor_external; + DpmActivityMonitorCoeffInt_t *activity_monitor = + &(activity_monitor_external.DpmActivityMonitorCoeffInt); ++ uint32_t profile_mode = input[size]; + int workload_type, ret = 0; + +- smu->power_profile_mode = input[size]; +- +- if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) { +- dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode); ++ if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) { ++ dev_err(smu->adev->dev, "Invalid power profile mode %d\n", profile_mode); + return -EINVAL; + } + +- if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { ++ if (enable && profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { + if (size != 10) + return -EINVAL; + +@@ -1783,16 +1784,18 @@ static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long * + /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ + workload_type = smu_cmn_to_asic_specific_index(smu, + CMN2ASIC_MAPPING_WORKLOAD, +- smu->power_profile_mode); ++ profile_mode); + if (workload_type < 0) + return -EINVAL; + ++ if (enable) ++ smu->workload_mask |= (1 << workload_type); ++ else ++ smu->workload_mask &= ~(1 << workload_type); + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask, + smu->workload_mask, NULL); + if (ret) + dev_err(smu->adev->dev, "[%s] Failed to set work load mask!", __func__); +- else +- smu_cmn_assign_power_profile(smu); + + return ret; + } +diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c +index 952ee22cbc90..a123ae7809ec 100644 +--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c +@@ -1054,7 +1054,8 @@ static int vangogh_get_power_profile_mode(struct smu_context *smu, + return size; + } + +-static int vangogh_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size) ++static int vangogh_set_power_profile_mode(struct smu_context *smu, long *input, ++ uint32_t size, bool enable) + { + int workload_type, ret; + uint32_t profile_mode = input[size]; +@@ -1065,7 +1066,7 @@ static int vangogh_set_power_profile_mode(struct smu_context *smu, long *input, + } + + if (profile_mode == PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT || +- profile_mode == PP_SMC_POWER_PROFILE_POWERSAVING) ++ profile_mode == PP_SMC_POWER_PROFILE_POWERSAVING) + return 0; + + /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ +@@ -1078,18 +1079,18 @@ static int vangogh_set_power_profile_mode(struct smu_context *smu, long *input, + return -EINVAL; + } + ++ if (enable) ++ smu->workload_mask |= (1 << workload_type); ++ else ++ smu->workload_mask &= ~(1 << workload_type); + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ActiveProcessNotify, + smu->workload_mask, + NULL); +- if (ret) { ++ if (ret) + dev_err_once(smu->adev->dev, "Fail to set workload type %d\n", + workload_type); +- return ret; +- } +- +- smu_cmn_assign_power_profile(smu); + +- return 0; ++ return ret; + } + + static int vangogh_set_soft_freq_limited_range(struct smu_context *smu, +diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c +index 62316a6707ef..25779abc5447 100644 +--- a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c +@@ -862,7 +862,8 @@ static int renoir_force_clk_levels(struct smu_context *smu, + return ret; + } + +-static int renoir_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size) ++static int renoir_set_power_profile_mode(struct smu_context *smu, long *input, ++ uint32_t size, bool enable) + { + int workload_type, ret; + uint32_t profile_mode = input[size]; +@@ -873,7 +874,7 @@ static int renoir_set_power_profile_mode(struct smu_context *smu, long *input, u + } + + if (profile_mode == PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT || +- profile_mode == PP_SMC_POWER_PROFILE_POWERSAVING) ++ profile_mode == PP_SMC_POWER_PROFILE_POWERSAVING) + return 0; + + /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ +@@ -889,17 +890,17 @@ static int renoir_set_power_profile_mode(struct smu_context *smu, long *input, u + return -EINVAL; + } + ++ if (enable) ++ smu->workload_mask |= (1 << workload_type); ++ else ++ smu->workload_mask &= ~(1 << workload_type); + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ActiveProcessNotify, + smu->workload_mask, + NULL); +- if (ret) { ++ if (ret) + dev_err_once(smu->adev->dev, "Fail to set workload type %d\n", workload_type); +- return ret; +- } + +- smu_cmn_assign_power_profile(smu); +- +- return 0; ++ return ret; + } + + static int renoir_set_peak_clock_by_device(struct smu_context *smu) +diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c +index 5dd7ceca64fe..6861267b68fb 100644 +--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c +@@ -2479,22 +2479,22 @@ static int smu_v13_0_0_get_power_profile_mode(struct smu_context *smu, + + static int smu_v13_0_0_set_power_profile_mode(struct smu_context *smu, + long *input, +- uint32_t size) ++ uint32_t size, ++ bool enable) + { + DpmActivityMonitorCoeffIntExternal_t activity_monitor_external; + DpmActivityMonitorCoeffInt_t *activity_monitor = + &(activity_monitor_external.DpmActivityMonitorCoeffInt); ++ uint32_t profile_mode = input[size]; + int workload_type, ret = 0; + u32 workload_mask; + +- smu->power_profile_mode = input[size]; +- +- if (smu->power_profile_mode >= PP_SMC_POWER_PROFILE_COUNT) { +- dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode); ++ if (profile_mode >= PP_SMC_POWER_PROFILE_COUNT) { ++ dev_err(smu->adev->dev, "Invalid power profile mode %d\n", profile_mode); + return -EINVAL; + } + +- if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { ++ if (enable && profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { + if (size != 9) + return -EINVAL; + +@@ -2547,13 +2547,18 @@ static int smu_v13_0_0_set_power_profile_mode(struct smu_context *smu, + /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ + workload_type = smu_cmn_to_asic_specific_index(smu, + CMN2ASIC_MAPPING_WORKLOAD, +- smu->power_profile_mode); ++ profile_mode); + + if (workload_type < 0) + return -EINVAL; + + workload_mask = 1 << workload_type; + ++ if (enable) ++ smu->workload_mask |= workload_mask; ++ else ++ smu->workload_mask &= ~workload_mask; ++ + /* Add optimizations for SMU13.0.0/10. Reuse the power saving profile */ + if ((amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 0) && + ((smu->adev->pm.fw_version == 0x004e6601) || +@@ -2564,25 +2569,13 @@ static int smu_v13_0_0_set_power_profile_mode(struct smu_context *smu, + CMN2ASIC_MAPPING_WORKLOAD, + PP_SMC_POWER_PROFILE_POWERSAVING); + if (workload_type >= 0) +- workload_mask |= 1 << workload_type; ++ smu->workload_mask |= 1 << workload_type; + } + +- smu->workload_mask |= workload_mask; + ret = smu_cmn_send_smc_msg_with_param(smu, + SMU_MSG_SetWorkloadMask, + smu->workload_mask, + NULL); +- if (!ret) { +- smu_cmn_assign_power_profile(smu); +- if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_POWERSAVING) { +- workload_type = smu_cmn_to_asic_specific_index(smu, +- CMN2ASIC_MAPPING_WORKLOAD, +- PP_SMC_POWER_PROFILE_FULLSCREEN3D); +- smu->power_profile_mode = smu->workload_mask & (1 << workload_type) +- ? PP_SMC_POWER_PROFILE_FULLSCREEN3D +- : PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; +- } +- } + + return ret; + } +diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c +index 9d0b19419de0..bf1f8e63e228 100644 +--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c +@@ -2434,22 +2434,23 @@ do { \ + return result; + } + +-static int smu_v13_0_7_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size) ++static int smu_v13_0_7_set_power_profile_mode(struct smu_context *smu, ++ long *input, uint32_t size, ++ bool enable) + { + + DpmActivityMonitorCoeffIntExternal_t activity_monitor_external; + DpmActivityMonitorCoeffInt_t *activity_monitor = + &(activity_monitor_external.DpmActivityMonitorCoeffInt); ++ uint32_t profile_mode = input[size]; + int workload_type, ret = 0; + +- smu->power_profile_mode = input[size]; +- +- if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_WINDOW3D) { +- dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode); ++ if (profile_mode > PP_SMC_POWER_PROFILE_WINDOW3D) { ++ dev_err(smu->adev->dev, "Invalid power profile mode %d\n", profile_mode); + return -EINVAL; + } + +- if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { ++ if (enable && profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { + if (size != 8) + return -EINVAL; + +@@ -2496,17 +2497,19 @@ static int smu_v13_0_7_set_power_profile_mode(struct smu_context *smu, long *inp + /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ + workload_type = smu_cmn_to_asic_specific_index(smu, + CMN2ASIC_MAPPING_WORKLOAD, +- smu->power_profile_mode); ++ profile_mode); + if (workload_type < 0) + return -EINVAL; + ++ if (enable) ++ smu->workload_mask |= (1 << workload_type); ++ else ++ smu->workload_mask &= ~(1 << workload_type); + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask, + smu->workload_mask, NULL); + + if (ret) + dev_err(smu->adev->dev, "[%s] Failed to set work load mask!", __func__); +- else +- smu_cmn_assign_power_profile(smu); + + return ret; + } +diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c +index d9f0e7f81ed7..cc9c42df2355 100644 +--- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c +@@ -1437,21 +1437,21 @@ static int smu_v14_0_2_get_power_profile_mode(struct smu_context *smu, + + static int smu_v14_0_2_set_power_profile_mode(struct smu_context *smu, + long *input, +- uint32_t size) ++ uint32_t size, ++ bool enable) + { + DpmActivityMonitorCoeffIntExternal_t activity_monitor_external; + DpmActivityMonitorCoeffInt_t *activity_monitor = + &(activity_monitor_external.DpmActivityMonitorCoeffInt); ++ uint32_t profile_mode = input[size]; + int workload_type, ret = 0; + +- smu->power_profile_mode = input[size]; +- +- if (smu->power_profile_mode >= PP_SMC_POWER_PROFILE_COUNT) { +- dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode); ++ if (profile_mode >= PP_SMC_POWER_PROFILE_COUNT) { ++ dev_err(smu->adev->dev, "Invalid power profile mode %d\n", profile_mode); + return -EINVAL; + } + +- if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { ++ if (enable && profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { + if (size != 9) + return -EINVAL; + +@@ -1504,15 +1504,16 @@ static int smu_v14_0_2_set_power_profile_mode(struct smu_context *smu, + /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ + workload_type = smu_cmn_to_asic_specific_index(smu, + CMN2ASIC_MAPPING_WORKLOAD, +- smu->power_profile_mode); ++ profile_mode); + if (workload_type < 0) + return -EINVAL; + ++ if (enable) ++ smu->workload_mask |= (1 << workload_type); ++ else ++ smu->workload_mask &= ~(1 << workload_type); + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask, +- smu->workload_mask, NULL); +- +- if (!ret) +- smu_cmn_assign_power_profile(smu); ++ smu->workload_mask, NULL); + + return ret; + } +diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c +index bdfc5e617333..91ad434bcdae 100644 +--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c +@@ -1138,14 +1138,6 @@ int smu_cmn_set_mp1_state(struct smu_context *smu, + return ret; + } + +-void smu_cmn_assign_power_profile(struct smu_context *smu) +-{ +- uint32_t index; +- index = fls(smu->workload_mask); +- index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; +- smu->power_profile_mode = smu->workload_setting[index]; +-} +- + bool smu_cmn_is_audio_func_enabled(struct amdgpu_device *adev) + { + struct pci_dev *p = NULL; +diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h +index 8a801e389659..1de685defe85 100644 +--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h +@@ -130,8 +130,6 @@ void smu_cmn_init_soft_gpu_metrics(void *table, uint8_t frev, uint8_t crev); + int smu_cmn_set_mp1_state(struct smu_context *smu, + enum pp_mp1_state mp1_state); + +-void smu_cmn_assign_power_profile(struct smu_context *smu); +- + /* + * Helper function to make sysfs_emit_at() happy. Align buf to + * the current page boundary and record the offset. diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index f68a41eeb1fa..6cd386d0fccb 100644 --- a/drivers/gpu/drm/drm_edid.c @@ -11464,9 +12187,9 @@ index f68a41eeb1fa..6cd386d0fccb 100644 -- 2.47.0 -From f16d50e4fc59e2c7f3ef308730ba77afdcac2878 Mon Sep 17 00:00:00 2001 +From aaf8a7e89d3582be8c14392fc4fe8c4cbd416ae2 Mon Sep 17 00:00:00 2001 From: Peter Jung -Date: Fri, 8 Nov 2024 17:36:26 +0100 +Date: Thu, 14 Nov 2024 17:00:14 +0100 Subject: [PATCH 07/13] intel-pstate Signed-off-by: Peter Jung @@ -11948,9 +12671,9 @@ index 348a330678bd..c11be253bfa3 100644 -- 2.47.0 -From c0242f5a4a52500a19004b54029c624bc2f36433 Mon Sep 17 00:00:00 2001 +From f75fb6bf2396dbc37335298fe042fad859df9fa8 Mon Sep 17 00:00:00 2001 From: Peter Jung -Date: Fri, 8 Nov 2024 17:37:00 +0100 +Date: Thu, 14 Nov 2024 17:01:43 +0100 Subject: [PATCH 08/13] ksm Signed-off-by: Peter Jung @@ -12381,9 +13104,9 @@ index 01071182763e..7394bad8178e 100644 -- 2.47.0 -From 3b74aac80ad5d4d1bc6b73c6050634865d58f0cd Mon Sep 17 00:00:00 2001 +From ee5a4d9bc72076794698e6e1da3ef217023f469c Mon Sep 17 00:00:00 2001 From: Peter Jung -Date: Fri, 8 Nov 2024 17:37:17 +0100 +Date: Thu, 14 Nov 2024 17:03:09 +0100 Subject: [PATCH 09/13] ntsync Signed-off-by: Peter Jung @@ -15470,9 +16193,9 @@ index 000000000000..5fa2c9a0768c -- 2.47.0 -From 9ddf5856d1be7d4bd93ca2cca7a9c21337969c6d Mon Sep 17 00:00:00 2001 +From 5f6d644590a3af5cc049db4d4b0c74d2ee29b58d Mon Sep 17 00:00:00 2001 From: Peter Jung -Date: Fri, 8 Nov 2024 17:37:42 +0100 +Date: Thu, 14 Nov 2024 17:08:15 +0100 Subject: [PATCH 10/13] perf-per-core Signed-off-by: Peter Jung @@ -16360,9 +17083,9 @@ index 8277c64f88db..b5a5e1411469 100644 -- 2.47.0 -From b87a889f2caa3af28aace25417833dd8e24b7254 Mon Sep 17 00:00:00 2001 +From a2687434017f228f18a7159b0b9af7f7ab2ef86a Mon Sep 17 00:00:00 2001 From: Peter Jung -Date: Fri, 8 Nov 2024 17:38:09 +0100 +Date: Thu, 14 Nov 2024 17:03:40 +0100 Subject: [PATCH 11/13] t2 Signed-off-by: Peter Jung @@ -18304,7 +19027,7 @@ index 000000000000..c26b7a19a5e4 +MODULE_DESCRIPTION("MacBookPro Touch Bar Keyboard Mode Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/hid/hid-core.c b/drivers/hid/hid-core.c -index 988d0acbdf04..caeba5487b69 100644 +index 3fcf098f4f56..a7ff0840afb5 100644 --- a/drivers/hid/hid-core.c +++ b/drivers/hid/hid-core.c @@ -1912,6 +1912,31 @@ int hid_set_field(struct hid_field *field, unsigned offset, __s32 value) @@ -26775,9 +27498,9 @@ index 4427572b2477..b60c99d61882 100755 -- 2.47.0 -From f59885cb7f117db011ba4e019cdbaef99f6ea4ab Mon Sep 17 00:00:00 2001 +From 31a90f4484502aa2a823c9946337db1d3f19511b Mon Sep 17 00:00:00 2001 From: Peter Jung -Date: Fri, 8 Nov 2024 17:38:31 +0100 +Date: Thu, 14 Nov 2024 17:04:02 +0100 Subject: [PATCH 12/13] thp-shrinker Signed-off-by: Peter Jung @@ -26939,7 +27662,7 @@ index 747943bc8cc2..d35e588e0ece 100644 THP_SCAN_EXCEED_NONE_PTE, THP_SCAN_EXCEED_SWAP_PTE, diff --git a/mm/huge_memory.c b/mm/huge_memory.c -index e44508e46e89..2b39915598a0 100644 +index a4d0dbb04ea7..187fd532ca10 100644 --- a/mm/huge_memory.c +++ b/mm/huge_memory.c @@ -73,6 +73,7 @@ static unsigned long deferred_split_count(struct shrinker *shrink, @@ -27040,7 +27763,7 @@ index e44508e46e89..2b39915598a0 100644 ret = -EAGAIN; } -@@ -3277,12 +3304,16 @@ void __folio_undo_large_rmappable(struct folio *folio) +@@ -3294,6 +3321,9 @@ bool __folio_unqueue_deferred_split(struct folio *folio) spin_lock_irqsave(&ds_queue->split_queue_lock, flags); if (!list_empty(&folio->_deferred_list)) { ds_queue->split_queue_len--; @@ -27048,8 +27771,10 @@ index e44508e46e89..2b39915598a0 100644 + __folio_clear_partially_mapped(folio); + } list_del_init(&folio->_deferred_list); + unqueued = true; } - spin_unlock_irqrestore(&ds_queue->split_queue_lock, flags); +@@ -3302,7 +3332,8 @@ bool __folio_unqueue_deferred_split(struct folio *folio) + return unqueued; /* useful for debug warnings */ } -void deferred_split_folio(struct folio *folio) @@ -27058,7 +27783,7 @@ index e44508e46e89..2b39915598a0 100644 { struct deferred_split *ds_queue = get_deferred_split_queue(folio); #ifdef CONFIG_MEMCG -@@ -3297,6 +3328,9 @@ void deferred_split_folio(struct folio *folio) +@@ -3317,6 +3348,9 @@ void deferred_split_folio(struct folio *folio) if (folio_order(folio) <= 1) return; @@ -27066,9 +27791,9 @@ index e44508e46e89..2b39915598a0 100644 + return; + /* - * The try_to_unmap() in page reclaim path might reach here too, - * this may cause a race condition to corrupt deferred split queue. -@@ -3310,14 +3344,20 @@ void deferred_split_folio(struct folio *folio) + * Exclude swapcache: originally to avoid a corrupt deferred split + * queue. Nowadays that is fully prevented by mem_cgroup_swapout(); +@@ -3327,14 +3361,20 @@ void deferred_split_folio(struct folio *folio) if (folio_test_swapcache(folio)) return; @@ -27095,7 +27820,7 @@ index e44508e46e89..2b39915598a0 100644 list_add_tail(&folio->_deferred_list, &ds_queue->split_queue); ds_queue->split_queue_len++; #ifdef CONFIG_MEMCG -@@ -3342,6 +3382,39 @@ static unsigned long deferred_split_count(struct shrinker *shrink, +@@ -3359,6 +3399,39 @@ static unsigned long deferred_split_count(struct shrinker *shrink, return READ_ONCE(ds_queue->split_queue_len); } @@ -27135,7 +27860,7 @@ index e44508e46e89..2b39915598a0 100644 static unsigned long deferred_split_scan(struct shrinker *shrink, struct shrink_control *sc) { -@@ -3349,8 +3422,8 @@ static unsigned long deferred_split_scan(struct shrinker *shrink, +@@ -3366,8 +3439,8 @@ static unsigned long deferred_split_scan(struct shrinker *shrink, struct deferred_split *ds_queue = &pgdata->deferred_split_queue; unsigned long flags; LIST_HEAD(list); @@ -27146,7 +27871,7 @@ index e44508e46e89..2b39915598a0 100644 #ifdef CONFIG_MEMCG if (sc->memcg) -@@ -3365,6 +3438,9 @@ static unsigned long deferred_split_scan(struct shrinker *shrink, +@@ -3382,6 +3455,9 @@ static unsigned long deferred_split_scan(struct shrinker *shrink, list_move(&folio->_deferred_list, &list); } else { /* We lost race with folio_put() */ @@ -27156,7 +27881,7 @@ index e44508e46e89..2b39915598a0 100644 list_del_init(&folio->_deferred_list); ds_queue->split_queue_len--; } -@@ -3374,20 +3450,55 @@ static unsigned long deferred_split_scan(struct shrinker *shrink, +@@ -3391,20 +3467,55 @@ static unsigned long deferred_split_scan(struct shrinker *shrink, spin_unlock_irqrestore(&ds_queue->split_queue_lock, flags); list_for_each_entry_safe(folio, next, &list, _deferred_list) { @@ -27237,7 +27962,7 @@ index 4cba91ecf74b..ee490f1e7de2 100644 folio = NULL; diff --git a/mm/migrate.c b/mm/migrate.c -index 75b858bd6aa5..a43bad6bd4e0 100644 +index 5028f3788b67..ba7e5c035406 100644 --- a/mm/migrate.c +++ b/mm/migrate.c @@ -177,13 +177,57 @@ void putback_movable_pages(struct list_head *l) @@ -27420,7 +28145,7 @@ index 3d89847f01da..bcf689c3e297 100644 __folio_mod_stat(folio, -nr, -nr_pmdmapped); diff --git a/mm/vmscan.c b/mm/vmscan.c -index 83c66d0267c0..6f4a3ab7217d 100644 +index ac53e21d28e7..e5e9df01724d 100644 --- a/mm/vmscan.c +++ b/mm/vmscan.c @@ -1238,7 +1238,8 @@ static unsigned int shrink_folio_list(struct list_head *folio_list, @@ -27589,9 +28314,9 @@ index 9007c420d52c..2eaed8209925 100644 -- 2.47.0 -From c1b6dbd10a05045020ba333ab3045dd710d7f74f Mon Sep 17 00:00:00 2001 +From 12ada7074a5e88b71b4e7fbe5654ef130ead1cff Mon Sep 17 00:00:00 2001 From: Peter Jung -Date: Fri, 8 Nov 2024 17:38:45 +0100 +Date: Thu, 14 Nov 2024 17:04:15 +0100 Subject: [PATCH 13/13] zstd Signed-off-by: Peter Jung